-------------------------------------------------------------------------------
-- control_unit_ent.vhd
-------------------------------------------------------------------------------
--
-- This file is part of SKUMLI.
-- Copyright (C) 2011 Davide Giuseppe Monaco (black.ralkass@gmail.com)
--
-- SKUMLI is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- SKUMLI is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with SKUMLI.  If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
entity control_unit is

  port (
    -- input signals
    clk           : in  std_logic;                     -- clock
    rst           : in  std_logic;                     -- reset
    cc_rdy        : in  std_logic;                     -- cc ready
    opcode        : in  std_logic_vector(5 downto 0);  -- instruction opcode
     
    -- control signals
    m_pc_din_sel  : out std_logic_vector(1 downto 0);  -- mux pc data in
    cu_zero       : out std_logic;                     -- pc we alu zero
    branch        : out std_logic;
    pc_we_s       : out std_logic;                     -- pc we signal
    ca_addr_sel   : out std_logic_vector(1 downto 0);  -- mux cc address
    ca_we         : out std_logic;                     -- current address we
    m_cc_addr_sel : out std_logic;
    cc_rw         : out std_logic;                     -- cc read/write (L/H)
    cc_cs         : out std_logic;                     -- cc chip select
    md_we         : out std_logic;                     -- md we
    m_data_sel    : out std_logic;                     -- mux regfile data in
    ir_we         : out std_logic;                     -- ir we
    alu_out_we    : out std_logic;                     -- alu out we
    tg_we         : out std_logic;                     -- target we
    alu_op        : out std_logic_vector(1 downto 0);  -- alu operation
    m_opd_b_sel   : out std_logic_vector(1 downto 0);  -- mux alu operand b
    m_opd_a_sel   : out std_logic;                     -- mux alu operand a
    opd_b_we      : out std_logic;                     -- operand B register we
    opd_a_we      : out std_logic;                     -- operand A register we
    rf_we         : out std_logic;                     -- rf we
    m_rd_sel      : out std_logic                      -- mux rf RD in
  );

end control_unit;
